1. Field of the Invention
The present invention relates to a memory device, and more particularly, to an on-die termination (hereinafter referred to as ‘ODT’) circuit and method for a memory device.
2. Description of the Related Art
An increase in the operating speed of a synchronous memory device results in a need for the termination of a transmission line, which is connected to a data input/output pin of a synchronous memory device in a memory system. An interface of a double data rate synchronous DRAM (“DDR SDRAM”) is based on stub series terminated transceiver logic (“SSTL”) using a termination resistor R-term outside of a memory device, such as a memory device 100 as shown in FIG. 1. In addition to the termination resistor R-term, a voltage regulator is required to generate termination voltage Vtt, thereby increasing the costs for an increased speed memory system.
A rail-to-rail ODT system, as shown in FIG. 2, has been suggested to solve this problem by eliminating the requirement for a voltage regulator. The ODT system includes a memory device 200 including termination resistors R-term1 and R-term2, and controls connection of the termination resistors R-term1 and R-term2 using switch transistors S1 and S2. In detail, when a termination enable signal TE is activated to logic ‘high’, the switch transistors S1 and S2 are turned on to enable the ODT system. However, the ODT system is disadvantageous in that during the enabling of the ODT system, the path of an electric current is formed between a supply voltage VDD and ground voltage VSS, thereby increasing consumption of an on-chip DC current.
In the case of DRAM including more than about sixteen pins, if an ODT circuit is installed in each pin, the amount of electric current is very large when all of the ODT circuits are simultaneously enabled. In this case, the amount of electric current is almost equivalent to that of the electric current for operating DRAM. Therefore, the total power consumption of DRAM substantially increases.